// SPDX-License-Identifier: GPL-2.0+
/*
 *  Driver for AMBA serial ports
 *
 *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
 *
 *  Copyright 1999 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  Copyright (C) 2010 ST-Ericsson SA
 *
 * This is a generic driver for ARM AMBA-type serial ports.  They
 * have a lot of 16550-like features, but are not register compatible.
 * Note that although they do have CTS, DCD and DSR inputs, they do
 * not have an RI input, nor do they have DTR or RTS outputs.  If
 * required, these have to be supplied via some other means (eg, GPIO)
 * and hooked into this driver.
 */
#include <errno.h>
#include <utils/types.h>
#include <seminix/init.h>
#include <seminix/string.h>
#include <devices/serial.h>
#include <asm/processor.h>
#include <asm/io.h>

#define UART_PL01x_RSR_OE               0x08
#define UART_PL01x_RSR_BE               0x04
#define UART_PL01x_RSR_PE               0x02
#define UART_PL01x_RSR_FE               0x01

#define UART_PL01x_FR_TXFE              0x80
#define UART_PL01x_FR_RXFF              0x40
#define UART_PL01x_FR_TXFF              0x20
#define UART_PL01x_FR_RXFE              0x10
#define UART_PL01x_FR_BUSY              0x08
#define UART_PL01x_FR_TMSK              (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)

/*
 *  PL010 definitions
 *
 */
#define UART_PL010_CR_LPE               (1 << 7)
#define UART_PL010_CR_RTIE              (1 << 6)
#define UART_PL010_CR_TIE               (1 << 5)
#define UART_PL010_CR_RIE               (1 << 4)
#define UART_PL010_CR_MSIE              (1 << 3)
#define UART_PL010_CR_IIRLP             (1 << 2)
#define UART_PL010_CR_SIREN             (1 << 1)
#define UART_PL010_CR_UARTEN            (1 << 0)

#define UART_PL010_LCRH_WLEN_8          (3 << 5)
#define UART_PL010_LCRH_WLEN_7          (2 << 5)
#define UART_PL010_LCRH_WLEN_6          (1 << 5)
#define UART_PL010_LCRH_WLEN_5          (0 << 5)
#define UART_PL010_LCRH_FEN             (1 << 4)
#define UART_PL010_LCRH_STP2            (1 << 3)
#define UART_PL010_LCRH_EPS             (1 << 2)
#define UART_PL010_LCRH_PEN             (1 << 1)
#define UART_PL010_LCRH_BRK             (1 << 0)

#define UART_PL010_BAUD_460800            1
#define UART_PL010_BAUD_230400            3
#define UART_PL010_BAUD_115200            7
#define UART_PL010_BAUD_57600             15
#define UART_PL010_BAUD_38400             23
#define UART_PL010_BAUD_19200             47
#define UART_PL010_BAUD_14400             63
#define UART_PL010_BAUD_9600              95
#define UART_PL010_BAUD_4800              191
#define UART_PL010_BAUD_2400              383
#define UART_PL010_BAUD_1200              767

/*
 *  PL011 definitions
 *
 */
#define UART_PL011_LCRH_SPS             (1 << 7)
#define UART_PL011_LCRH_WLEN_8          (3 << 5)
#define UART_PL011_LCRH_WLEN_7          (2 << 5)
#define UART_PL011_LCRH_WLEN_6          (1 << 5)
#define UART_PL011_LCRH_WLEN_5          (0 << 5)
#define UART_PL011_LCRH_FEN             (1 << 4)
#define UART_PL011_LCRH_STP2            (1 << 3)
#define UART_PL011_LCRH_EPS             (1 << 2)
#define UART_PL011_LCRH_PEN             (1 << 1)
#define UART_PL011_LCRH_BRK             (1 << 0)

#define UART_PL011_CR_CTSEN             (1 << 15)
#define UART_PL011_CR_RTSEN             (1 << 14)
#define UART_PL011_CR_OUT2              (1 << 13)
#define UART_PL011_CR_OUT1              (1 << 12)
#define UART_PL011_CR_RTS               (1 << 11)
#define UART_PL011_CR_DTR               (1 << 10)
#define UART_PL011_CR_RXE               (1 << 9)
#define UART_PL011_CR_TXE               (1 << 8)
#define UART_PL011_CR_LPE               (1 << 7)
#define UART_PL011_CR_IIRLP             (1 << 2)
#define UART_PL011_CR_SIREN             (1 << 1)
#define UART_PL011_CR_UARTEN            (1 << 0)

#define UART_PL011_IMSC_OEIM            (1 << 10)
#define UART_PL011_IMSC_BEIM            (1 << 9)
#define UART_PL011_IMSC_PEIM            (1 << 8)
#define UART_PL011_IMSC_FEIM            (1 << 7)
#define UART_PL011_IMSC_RTIM            (1 << 6)
#define UART_PL011_IMSC_TXIM            (1 << 5)
#define UART_PL011_IMSC_RXIM            (1 << 4)
#define UART_PL011_IMSC_DSRMIM          (1 << 3)
#define UART_PL011_IMSC_DCDMIM          (1 << 2)
#define UART_PL011_IMSC_CTSMIM          (1 << 1)
#define UART_PL011_IMSC_RIMIM           (1 << 0)

struct pl01x_regs {
    u32	dr;		/* 0x00 Data register */
    u32	ecr;		/* 0x04 Error clear register (Write) */
    u32	pl010_lcrh;	/* 0x08 Line control register, high byte */
    u32	pl010_lcrm;	/* 0x0C Line control register, middle byte */
    u32	pl010_lcrl;	/* 0x10 Line control register, low byte */
    u32	pl010_cr;	/* 0x14 Control register */
    u32	fr;		/* 0x18 Flag register (Read only) */
    u32	pl011_rlcr;	/* 0x1c Receive line control register */
    u32	ilpr;		/* 0x20 IrDA low-power counter register */
    u32	pl011_ibrd;	/* 0x24 Integer baud rate register */
    u32	pl011_fbrd;	/* 0x28 Fractional baud rate register */
    u32	pl011_lcrh;	/* 0x2C Line control register */
    u32	pl011_cr;	/* 0x30 Control register */
};

enum pl01x_type {
    TYPE_PL010,
    TYPE_PL011,
};

struct amba_pl01x_data {
    struct pl01x_regs *base_regs;
    enum pl01x_type pl01x_type;
};

static struct amba_pl01x_data pl01x_data;

static void pl01x_putc(struct pl01x_regs *regs, char c)
{
    /* Wait until there is space in the FIFO */
    while(readl(&regs->fr) & UART_PL01x_FR_TXFF)
        cpu_relax();

    /* Send the character */
    writel(c, &regs->dr);

    while(readl(&regs->fr) & UART_PL01x_FR_BUSY)
        cpu_relax();
}

static void pl01x_console_write(struct console_device *dev, const char *s, unsigned int n)
{
    unsigned int i;
    struct amba_pl01x_data *data = (struct amba_pl01x_data *)dev->private_data;
    struct pl01x_regs *regs = data->base_regs;

    for (i = 0; i < n; i++, s++) {
        if (*s == '\n')
            pl01x_putc(regs, '\r');
        pl01x_putc(regs, *s);
    }
}

static int __init pl01x_generic_serial_init(struct pl01x_regs *regs,
                     enum pl01x_type type)
{
    switch (type) {
    case TYPE_PL010:
        /* disable everything */
        writel(0, &regs->pl010_cr);
        break;
    case TYPE_PL011:
        /* disable everything */
        writel(0, &regs->pl011_cr);
        break;
    default:
        return -EINVAL;
    }

    return 0;
}

static int __init pl011_set_line_control(struct pl01x_regs *regs)
{
    unsigned int lcr;
    /*
     * Internal update of baud rate register require line
     * control register write
     */
    lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
    writel(lcr, &regs->pl011_lcrh);
    return 0;
}

static int __init pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
                int clock, int baudrate)
{
    switch (type) {
    case TYPE_PL010: {
        unsigned int divisor;

        /* disable everything */
        writel(0, &regs->pl010_cr);

        switch (baudrate) {
        case 9600:
            divisor = UART_PL010_BAUD_9600;
            break;
        case 19200:
            divisor = UART_PL010_BAUD_19200;
            break;
        case 38400:
            divisor = UART_PL010_BAUD_38400;
            break;
        case 57600:
            divisor = UART_PL010_BAUD_57600;
            break;
        case 115200:
            divisor = UART_PL010_BAUD_115200;
            break;
        default:
            divisor = UART_PL010_BAUD_38400;
        }

        writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
        writel(divisor & 0xff, &regs->pl010_lcrl);

        /*
         * Set line control for the PL010 to be 8 bits, 1 stop bit,
         * no parity, fifo enabled
         */
        writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
               &regs->pl010_lcrh);
        /* Finally, enable the UART */
        writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
        break;
    }
    case TYPE_PL011: {
        unsigned int temp;
        unsigned int divider;
        unsigned int remainder;
        unsigned int fraction;

        /*
        * Set baud rate
        *
        * IBRD = UART_CLK / (16 * BAUD_RATE)
        * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
        *		/ (16 * BAUD_RATE))
        */
        temp = 16 * baudrate;
        divider = clock / temp;
        remainder = clock % temp;
        temp = (8 * remainder) / baudrate;
        fraction = (temp >> 1) + (temp & 1);

        writel(divider, &regs->pl011_ibrd);
        writel(fraction, &regs->pl011_fbrd);

        pl011_set_line_control(regs);
        /* Finally, enable the UART */
        writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
               UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
        break;
    }
    default:
        return -EINVAL;
    }

    return 0;
}

static void __init pl01x_console_init(struct console_device *dev)
{
    struct amba_pl01x_data *data = (struct amba_pl01x_data *)dev->private_data;
    struct pl01x_regs *regs = data->base_regs;

    pl01x_generic_serial_init(regs, data->pl01x_type);
    pl01x_generic_setbrg(regs, data->pl01x_type, dev->clk, dev->baud);
}



static int __init pl01x_console_setup(struct console_device *device,
                        const char *opt)
{
    if (!device->membase)
        return -ENODEV;

    pl01x_data.base_regs = (struct pl01x_regs *)device->membase;
    if (strncmp(device->compatible, "arm,pl011", strlen("arm,pl011")) == 0)
        pl01x_data.pl01x_type = TYPE_PL011;
    else
        pl01x_data.pl01x_type = TYPE_PL010;

    device->write = pl01x_console_write;
    device->private_data = (void *)&pl01x_data;

    pl01x_console_init(device);

    return 0;
}
OF_CONSOLE_DECLARE(pl011, "arm,pl011", pl01x_console_setup);
OF_CONSOLE_DECLARE(pl010, "arm,pl010", pl01x_console_setup);
